This invention relates to a semiconductor device microminiaturized by a submicron fabrication technique and, in particular, a high packing density semiconductor integrated circuit having field effect transistors of submicron size and a method for manufacturing the same.
With a recent advance in the microminiaturizing technology, semiconductor IC (integrated circuit) devices have been manufactured with field effect transistors formed in a chip substrate and their effective channel length defined on the order of submicron size. The submicron fabricating technique is the most promising, basic technical approach to satisfying an unending desire for the improvement of a semiconductor memory integration. Various techniques have been developed to implement a microminiaturized transistor pattern on a chip substrate, while securing high reliability and high yield.
The microminiaturization of transistors in the semiconductor device involves various problems of, for example, degrading a basic device performance. The submicron field effect transistors, such as metal oxide semiconductor field effect transistors (hereinafter referred to as MOSFETs) suffer from the drawbacks of involving a punch-through phenomenon across a source-to-drain circuit and of lowering a junction breakdown voltage on active layers acting as a source and drain. In the microminiaturized MOSFETs, an effective channel length is short due to a short source-to-drain distance. With an increasing voltage applied to the active layers, depletion layers around the active layers are enlarged in the semiconductive substrate. When the voltage applied exceeds a certain level, the depletion layers become joined together. In such a punch-through state, the basic transistor action is impeded. Where the effective channel length is short on the order of submicron size, the punch-through phenomenon is more liable to occur in an extremely prominent fashion, posing a serious problem to the microminiaturized MOSFETs.
With the impurity concentration of the substrate set at a high level, it is possible to suppress the extending of the depletion layers around the active layer in the substrate, and thus minimizing the generation of the aforementioned punch-through phenomenon. In this case, however, an impurity concentration difference between the active layer and the substrate becomes naturally larger, resulting in another problem of decreasing the junction breakdown voltage at the source and the drain. If the junction breakdown voltage on the MOSFETs is degraded, the operation margin of the MOSFET is lowered, thereby degrading the basic performance of the IC device.
In consideration of these factors, it has recently been proposed to provide MOSFETs having a lightly doped drain structure which is known in the art as an LDD structure. According to this structure, the lightly doped semiconductor layers of the same conductivity type as those of the active layers are formed around the periphery of the active layers (the source and drain) in the substrate. These layers have an impurity concentration level which is lower than those of the active layers. Even in the semiconductor devices of this structure, however, it has been difficult to solve the aforementioned conflicting problems at once, since, if the lightly doped layer is so formed as to be partially joined to each active layer at a channel region, it is not possible to suppress the lowering of a junction breakdown voltage on a location between the lightly doped layer and the remaining portion of the active layer. If, on the other hand, the lightly doped layer is so formed as to fully surround each active layer, then the occurrence of the punch-through phenomenon cannot be properly suppressed to a desired extent since the junction depth of the lightly doped layer is greater.